The present invention relates to a semiconductor device including a p-channel transistor and an n-channel transistor each of which has a multi-finger structure.
As electronic devices have been downsized and manufactured at lower cost, power transistors that are mounted on such electronic devices are also required to be downsized. In particular, electronic devices that operate at breakdown voltages of 100 V or lower, such as portable devices and household appliances, are required to be further downsized and manufactured at lower costs. A drive circuit mounted on such an electronic device includes a p-channel transistor and an n-channel transistor that are integrated on the same chip.
In the prior art, when a p-channel transistor and an n-channel transistor are integrated on the same chip, the two transistors are arranged in a manner that their carriers move in the same direction due to aspects related with the manufacturing cost and manufacturing equipments. However, the n-channel transistor and the p-channel transistor differ from each other in their crystal plane and crystal axis when mobility of their carriers becomes maximal. In the field of logic large scale integration (LSI), an output circuit is typically formed by connecting a p-channel transistor and an n-channel transistor in a complementary manner. In this case, in the prior art, the output circuit changes channel formation planes (crystal planes) or channel directions (crystal axes) between the n-channel transistor and the p-channel transistor. This technique is described, for example, in Japanese Laid-Open Patent Publication No. 63-80561 and the literature listed below:
H. Sayama et al., “Effect of <100> Channel Direction for High Performance SCE Immune PMOSFET with Less than 0.15 um Gate Length”, International Electron Devices Meeting (IEDM) Technology Digest (1999), p. 657.
H. Momose et al., “110 GHz Cutoff Frequency of Ultra-thin Gate Oxide P-MOSFETs on (110) Surface-oriented Si Substrate”, 2002 Symposium on VLSI Technology Digest of Technical Papers, IEEE (2002).
For example, the literature by H. Momose et al. describes planer transistors, and improves mobility of carriers of both an n-channel transistor and a p-channel transistor by arranging the two transistors in a manner that their channel directions intersect with each other at an angle of 45 degrees.
A lateral double diffused metal oxide semiconductor field effect transistor (hereafter referred to as “LDMOSFET”) is a known transistor structure that facilitates integration of a plurality of power transistors. The LDMOSFET is also effective as a structure for integrating the above-described n-channel transistor and p-channel transistor on the same chip. As such, the LDMOSFET has been widely commercialized.
The LDMOSFET normally has a drift region formed close to the drain to increase the breakdown voltage. The drift region typically requires a length of about 0.067 μm/V. For example, to manufacture an LDMOSFET having a breakdown voltage of 40 V, a drift region having a length of about 3 micrometers must be formed using a submicron fabrication technique. The pitch between the source and drain of the LDMOSFET must be at least 5 micrometers to include contacts connected to metal wires and elements such as gate electrodes. Further, a power transistor mounted on a drive circuit must have an extremely wide gate width to minimize on-resistance during switching. Thus, such a power transistor employs a multi-finger structure in which sources and drains are arranged in parallel in the direction of the gate length (channel direction) of the transistor. In the multi-finger structure, the sources and drains are alternately with gates located in between. The multi-finger structure has a plurality of parallel gates arranged in parallel to increase the total gate width of the transistor. However, the multi-finger structure causes the power transistor to occupy a relatively large area on the chip.
Further, a semiconductor device including an n-channel transistor and p-channel transistor having multi-finger structures may have the problem described below when the n-channel transistor and the p-channel transistor are configured to improve carrier mobility in both transistors.
Elements arranged on a main surface of a semiconductor substrate are usually formed in a rectangular region of which sides are parallel to the four sides of a semiconductor chip so that the elements do not increase the chip area in an unnecessary manner. When, for example, a p-channel transistor is arranged in a manner that its gate width direction is at an angle of 45 degrees with respect to the gate width direction of an n-channel transistor, the gate width direction of the p-channel transistor intersects with one side of the rectangular area at an angle of 45 degrees. This arrangement generates an ineffective region that fails to contribute to increasing the gate width of the transistor within the region in which the p-channel transistor is formed. In this case, the specific on-resistance (on-resistance*area) of the transistor cannot be decreased by an amount corresponding to the ineffective region. As a result, even if the n-channel transistor and the p-channel transistor of the semiconductor device are arranged to have different crystal planes and different crystal axes to improve mobility of carriers of the two transistors, the semiconductor device may not always be able to improve performance when the two transistors are formed on the same chip.